What a board review actually catches

Every board we send to fab gets read by someone who did not draw it. It adds a day. It has saved us more respins than any simulation we have ever run.

The pattern we keep seeing: the schematic is fine. The circuit works. What kills the board is something nobody thought to check because it lives between two disciplines.

The list

Test points on anything you cannot probe. If a rail is under a connector or a shield can, it does not exist as far as bring-up is concerned. Two cents of copper now versus scraping soldermask with a scalpel later.

Connector orientation against the enclosure. A USB-C port two millimetres inboard of where the CAD model says is a new enclosure, not a new board. This one is worth checking against the actual STEP file, not the drawing.

Decoupling that survives placement. Everyone puts 100nF next to the pin in the schematic. Half the time the layout ends up with it 8mm away on the far side of a via. The schematic reviewer and the layout reviewer have to be looking at the same thing.

Thermal reliefs on ground pads. A regulator tab tied straight into a pour is a joint your assembly house cannot reflow evenly. It passes AOI and fails six months later.

Silkscreen that means something. Pin 1 markers, polarity, connector labels. Nobody needs it until someone else assembles the board at 11pm.

Bill of materials against real stock. Not “is this part in the library” but “can we buy four hundred of it in nine weeks”. We check lead times at review, not at order.

Why not automate it

Most of these have a DRC rule somewhere. We run those too. But the failures that cost real money are judgement calls — is this test point in a place a human hand can reach, is this part going to be available when we actually need it — and a rule set does not have an opinion about that.

The review is cheap. A respin is four weeks and a fab bill. We have never once regretted the day.